1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device having a built-in cache memory and an access method and a memory control system for the same.
2. Description of the Related Art
In recent years, demand for NAND type flash memories and other block access type semiconductor memories has been rapidly growing.
FIG. 1 is a view of an example of the internal configuration of an example of a block access type memory, that is, a NAND type flash memory. The NAND type flash memory of FIG. 1 has a plurality of memory units 1-1 to 1-n connected to bit lines BL1 to BLn and arrayed in an array (vertically and laterally). The memory units 1 (-1 to -n) are sandwiched between selection transistors 2 and 3 and include for example 16 memory cells N0 to N15 connected in series. For example, gates of the selection transistors 2 and 3 in odd number columns are connected to selection gate lines SL1 and SL2, while gates of the selection transistors 2 and 3 in even number columns are connected to selection gate lines SL3 and SL4. Further, the gates of the memory cells N0 to N15 are connected to word lines WL0 to WL15.
The memory cells N0 to N15 have multilayer gate structures and store data according to the charges built up in the floating gates. Namely, when many electrons build up in a floating gate, the threshold value of the transistor rises, therefore any current penetration through the memory units 1 (-1 to -n) from the charged bit lines BL1 to BLn is detected at an access circuit 4 including a sense amplifier, etc. and the data is judged.
In such a NAND type flash memory, no contact to the bit line for each memory cell is necessary, therefore the effective cell size can be reduced. This is also advantageous for reducing costs. However, a large number of cell transistors are connected in series, therefore the read current of each unit is very small. Further, in order to reduce peripheral circuits, the array becomes very large. The load capacitances of the word lines and the bit lines are large, and a long time is required for driving them. Accordingly, this is not suitable for random access in units of bytes or words. Either such specifications are not provided, or an access time of tens of μs is required. Namely, in order to produce such a memory cheaply, the access performance at the cell level is sacrificed.
However, the data of the large number of cells connected to a selected word line in the array is simultaneously read out by the sense amplifier in parallel. Therefore, an increase in speed is possible in block units of several kB. Namely, once header data is read, continuous data can be read at a high speed.
Further, the speed of write operations can be similarly increased by the same parallel processing. In, for example, a NAND type flash memory, a low current write operation by Fowler-Nordheim (F-N) injection is possible. Therefore, the speed of transfer in block units is faster than the speed of NOR type flash memories by close to 2 orders.
Such a memory is mainly used as a user file storage for portable phones, digital cameras, etc. at present.
FIG. 2 is a block diagram conceptually showing the system configuration when using flash memories for user file storage.
This system 10 is comprised of a central processing unit (CPU) 11, a NOR type flash memory 13, and a dynamic random access memory (DRAM) 14 connected via a system bus 12. Both memories are mapped as regions in the system memory. The NOR type flash memory 13 stores the boot code, operating system (OS), and applications. Further, the DRAM 14 is loaded with part of the applications for execution and forms a work area of the OS.
The system bus 12 is further connected to an interface circuit (IF) 15 for accessing an external memory device and the interface circuit 15 is connected to a control circuit 16 for controlling a NAND type flash memory 17. The control circuit 16 inputs/outputs and transfers data of the NAND type flash memory 17 matched with the specifications of the interface circuit 15 determined by ATA standard etc., and further has a function of converting a logical address designated from the outside to a physical address of the memory 17, a function of encoding and correcting errors of the data read out from the memory 17 at an ECC circuit, and other functions.
FIG. 3 is a view of an example of a memory map of the system of FIG. 2. In FIG. 3, 21 indicates the memory region of the NOR type flash memory 13, and 22 indicates the memory region of the DRAM 14.
When the system is started up, the CPU 11 accesses the NOR type flash memory region 21 first and executes the boot code 23 thereof. In that process, various types of programs are loaded into the DRAM region 22 from the NOR type flash memory region 21 for execution. For example, driver software 24 for operating the interface circuit 15 is loaded and executed. Access to the NAND type flash memory 17 becomes possible at that point of time. The flash memory 17 is not mapped to the system memory. An IO map space is separately provided, and data is transferred using a specific protocol prescribed by the interface circuit 15 and the driver software 24 via a register mapped there.
A long time is taken for extracting the desired portion of the block type data, therefore block device management software 25 is loaded and executed and a block data cache region 26 is secured and managed.
When the NAND type flash memory 17 becomes usable in this way, it is mainly used for storing user data as files. Further, parts of the applications are stored as files. These are sometimes loaded, opened up, and executed in empty regions in the DRAM 14.